1. Technical Field of the Invention
The present invention relates to constructions and manufacturing methods of semiconductor devices in which a p-channel and n-channel thin-film transistors are arranged on a common substrate. More particularly, the invention is concerned with circuit configurations and manufacturing methods of complementary metal oxide semiconductor (CMOS) devices comprising thin-film transistors arranged on a glass substrate.
2. Description of the Related Art
In one conventionally known technique used for producing a thin-film transistor, a silicon layer is formed on a glass substrate and this silicon layer is used for manufacturing the thin-film transistor. This prior art technique has evolved mostly in the industry of manufacturing active matrix liquid crystal display devices.
Generally, a liquid crystal display is so constructed that liquid crystal is sandwiched between a pair of glass substrates. When voltages are applied across the liquid crystal layer which constitutes a large number of pixels arranged in a matrix form, optical properties of the liquid crystal are varied. As a result, the liquid crystal display presents a picture corresponding to the applied voltages.
An active matrix liquid crystal display is generally so constructed that thin-film transistors are provided in the aforementioned pixels which are arranged in a matrix form. These thin-film transistors control electric charges which are fed into and output from the individual pixels.
A common construction of the active matrix liquid crystal display today is such that a circuit (which is referred to as a peripheral driver circuit) for driving thin-film transistors arranged in a few hundred rows by a few hundred columns in an active matrix area is composed essentially of an integrated circuit (a driver IC) which is connected to the outside of a glass substrate using tape automated bonding (TAB) technology, for instance.
One problem of this construction, in which the driver IC is externally mounted to the outside of a glass substrate, is that it requires a complicated process for producing active matrix liquid crystal displays. For example, alignment of each driver IC and operational tests become complicated. Another problem is that a projecting portion is created on each active matrix liquid crystal display when the driver IC is externally mounted. This will impair potential multi-purpose applicability of the active matrix liquid crystal displays in cases where they are to be assembled into various kinds of electronics apparatus.
An approach to the solution of the aforementioned problems is to integrally form a peripheral driver circuit itself with thin-film transistors directly on a glass substrate. This approach makes it possible to create an integrated device structure. Furthermore, it will provide such advantageous effects as simplification of manufacturing processes, increased reliability and greater applicability.
In an active matrix liquid crystal display having such an integrally formed peripheral driver circuit, a CMOS circuit is required to configure the peripheral driver circuit. The CMOS circuit is one of basic electronic circuits in which n- and p-channel transistors are joined together to form a complementary configuration.
An example of a conventional method of producing CMOS circuitry on a glass substrate is described with reference to FIGS. 4(A) to 4(D).
First, a silicon oxide film 402 which constitutes an underlying layer is grown on a glass substrate 401 as shown in FIG. 4(A). Then, active layers 403 and 404 which may either be crystalline or amorphous silicon layers are deposited on top of the silicon oxide film 402, and another silicon oxide film 405 which covers the active layers 403 and 404 and acts as a gate insulating layer is created. In FIG. 4(A), the active layer 403 is an islandlike region forming an active layer of an n-channel thin-film transistor while the active layer 404 is an islandlike region forming an active layer of a p-channel thin-film transistor.
Next, gate electrodes 406 and 407 composed of an electrically conductive material such as a silicide are formed as shown in FIG. 4(B), and phosphorus ions are implanted over the whole surface of the workpiece shown in FIG. 4(C). As a result, portions designated by the numerals 408, 410, 411 and 413 become n-type regions. The implantation of phosphorus ions is performed at a dose of 1.times.10.sup.15 /cm.sup.2 to 2.times.10.sup.15 /cm.sup.2 under conditions where a surface phosphorus ion density of 1.times.10.sup.20 /cm.sup.2 or over is achieved.
Subsequently, a resist mask 414 is formed to selectively cover the n-channel thin-film transistor and boron ions are implanted as shown in FIG. 4(D) at a dose three to five times higher than the aforesaid dose of phosphorus ions. This causes the n-type regions 411 and 413 (FIG. 4(C)) to turn to the opposite conductivity type, or p-type. A source region 415, a drain region 416 and a channel region 412 of the p-channel thin-film transistor are created in a self-aligned manner. The reason why such a heavy doping level as described above is required is that the regions 415, 412 and 416 must form a p-i-p junction. In the construction of FIG. 4(D), the numerals 408, 409 and 410 designate a source region, a channel region and a drain region of the n-channel thin-film transistor, respectively.
In the aforementioned production method there is no need to form a resist mask in the processing step shown in FIG. 4(C). Although this is advantageous for simplifying production process, the production method has the following problems.
First, the implantation of impurity ions into the resist mask 414 at an extremely high doping level causes resist materials to vary in their properties, and this will result in an increase in the probability of occurrence of failures in the production process. More specifically, it may become impossible to remove the resist materials after doping, or the resist materials may partially be left after a photoresist removal process.
Second, the existence of an off current flowing through a junction between the channel region 412 and drain region 416 can not be disregarded. This is because the drain region 416 adjacent to the channel region 412 of the p-channel thin-film transistor shown at right in FIG. 4(D) is a region doped with an extremely high concentration of impurities, in which the impurity ions are added at a far higher doping level than what is normally required for producing a p-channel device, in order to invert the conductivity type.
Third, the boron ions implanted are inevitably added to the channel region 412 in part due to their undesirable migration. This phenomenon gives rise to a problem that essential electrical properties are not obtained at all, or such electrical properties are often unattainable.
Fourth, the implantation of the impurity ions at a high doping level which is needed in the processing step shown in FIG. 4(D) may overload an ion implanter or a plasma doping machine. This is likely to arise various problems due to contamination inside the equipment and its maintenance.
A fifth problem is that the need for the implantation of the impurity ions at a high doping level may lead to an increase in processing time.
A sixth problem could develop when annealing a product by using laser light. Generally, the resist mask 414 is removed after the processing step shown in FIG. 4(D) is finished, and then an annealing process, in which a laser beam is irradiated upon the product, is required in order to activate the dopant and to anneal the regions where the impurity ions have been implanted. (This method is effective when a glass substrate having low thermal resistance is used.) Since the regions 415 and 416 are doped with far larger amounts of impurity ions compared to the regions 408 and 410, remarkable damage occurs in the crystallinity of the former regions. Consequently, the dependence of optical absorbance on wavelength greatly differs between the two groups of regions: the regions 408 and 410, and the regions 415 and 416. In this situation, the effect of annealing by the laser light also differs considerably between the two groups of regions. This is not preferable because a large difference in electrical properties will occur between the n-channel thin-film transistor and p-channel thin-film transistor shown at left and right in FIG. 4(D), respectively.